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| data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 environmental requirements: ? ? ? ? ? ? figure: mechanical dimensions 1 1gb ddr2 C sdram so - dimm 200 pin so - dimm sen01g64d1b f 1sa - xx r 1gbyte in fbga tech nology rohs compliant options: ? data rate / latency marking ddr2 667 mt/s cl5 - 30 ddr2 800 mt/ s cl6 - 25 ? module d ensity 1024mb with 8 dies and 1 rank ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c grade e (t a ) 0c to 85c (t c ) 0c to 95c grade w (t a ) - 40c to 85c (t c ) - 40c to 95c * the refresh rate has to be doubl ed when 85c>t c >95c features: ? 200 - pin 64 - bit small outline, dual - in - line double data rate s ynchronous dram module ? module organization: single rank 128 m x 64 ? v dd = 1.8v 0. 1 v, v ddq 1.8v 0.1 v ? 1.8v i/o ( sstl_18 compatible) ? auto refresh (cbr) and self ref resh 8k refresh every 64ms ? serial presence detect with eeprom ? gold - contact pad ? this module is fully pin and functional compatible to the jedec pc2 - 64 00 spec. and jedec - standard mo - 224 . (see www.jedec.org ) ? the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr2 - sdram component samsung k4t1g084qf die rev. f ? 128mx8 ddr2 sdram in fbga - 60 package ? four bit prefetch ar chitecture ? dll to align dq and dqs transitions with ck ? eight internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst length: 4 or 8 ? adjustable dat a - output drive strength ? on - die termination (odt) 1 if no tolerances specified 0.15mm
data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 this swissbit module is an industry standard 200 - pin 8 - byte ddr2 sdram small outline dual - in - line memo ry module (so - dimm) which is organized as x64 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr2 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr2 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high ef fective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the optional serial presence detect (spd) function implemented via se rial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the so - dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. t he second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank addr. column addr. refresh module bank select 128m x 64bit 8 x 128m x 8bit (1024mbit) 14 ba0, ba1,ba2 10 8k s0# module dimensi ons in mm 67.60 (long) x 30 (high) x 3.80 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sen01g64d1bf1sa - 25r 1024 mb 6.4 gb/s 2.5ns/800mt/s 6 - 6 - 6 sen01g64d1bf1sa - 30r 1024 mb 5.3 gb/s 3.0 ns/667mt/s 5 - 5 - 5 pin name a0 - 9, a11 C a13 address inputs a10/ap address input / autoprecharge bit ba0 C ba2 bank address inputs dq0 C dq63 data input / output dm0 - dm7 input data mask dqs0 - dqs7 data strobe, positive line dqs0# - dqs7# data strobe , negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 clock enable ck0 C ck1 clock inputs, positive line figure 1: mechanical dimensions data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ck0# C ck1# clock inputs, negative line s0# chip se lect v dd supply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0 on - d ie termination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 2 v ss 101 a1 102 a0 3 v ss 4 dq4 103 v dd 104 v dd 5 dq0 6 dq5 105 a10/ap 106 ba1 7 dq1 8 v ss 107 ba0 108 ras# 9 v ss 10 dm0 109 we# 110 s0# 11 dqs0# 12 v ss 111 v dd 112 v dd 13 dqs0 14 dq6 113 cas# 114 odt0 15 v ss 16 dq7 115 nc ( s1# ) 116 a13 17 dq2 18 v ss 117 v dd 118 v dd 19 dq3 20 dq12 119 nc ( odt1 ) 120 nc (s3) 21 v ss 22 dq13 121 v ss 122 v ss 23 dq8 24 v ss 123 dq32 124 dq36 25 dq9 26 dm1 125 dq33 126 dq37 27 v ss 28 v ss 127 v ss 128 v ss 29 dqs1# 30 ck0 129 dqs4# 130 dm4 31 dqs1 32 ck0# 131 dqs4 132 v ss 33 v ss 34 v ss 133 v ss 134 dq38 35 dq10 36 dq14 135 dq34 136 dq39 37 dq11 38 dq15 137 dq35 138 v ss 39 v ss 40 v ss 139 v s s 140 dq44 41 v ss 42 v ss 141 dq40 142 dq45 43 dq16 44 dq20 143 dq41 144 v ss 45 dq17 46 dq21 145 v ss 146 dqs5# 47 v ss 48 v ss 147 dm5 148 dqs5 49 dqs2# 50 nc (event#) 149 v ss 150 v ss 51 dqs2 52 dm2 151 dq42 152 dq46 data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 pin # front side pin # back side p in # front side pin # back side 53 v ss 54 v ss 153 dq43 154 dq47 55 dq18 56 dq22 155 v ss 156 v ss 57 dq19 58 dq23 157 dq48 158 dq52 59 v ss 60 v ss 159 dq49 160 dq53 61 dq24 62 dq28 161 v ss 162 v ss 63 dq25 64 dq29 163 nc (test) 164 nc( ck1 ) 65 v ss 66 v ss 165 v ss 166 nc( ck1# ) 67 dm3 68 dqs3# 167 dqs6# 168 v ss 69 nc (reset#) 70 dqs3 169 dqs6 170 dm6 71 v ss 72 v ss 171 v ss 172 v ss 73 dq26 74 dq30 173 dq50 174 dq54 75 dq27 76 dq31 175 dq51 176 dq55 77 v ss 78 v ss 177 v ss 178 v ss 79 cke0 80 nc ( cke1 ) 179 dq56 180 dq60 81 v dd 82 v dd 181 dq57 182 dq61 83 nc (s2#) 84 nc (a15) 183 v ss 184 v ss 85 ba2 86 nc (a14) 185 dm7 186 dqs7# 87 v dd 88 v dd 187 v ss 188 dqs7 89 a12 90 a11 189 dq58 190 v ss 91 a9 92 a7 191 dq59 192 dq62 93 a8 94 a6 193 v ss 194 dq63 95 v dd 96 v dd 195 sda 196 v ss 97 a5 98 a4 197 scl 198 sa0 99 a3 100 a2 199 v ddspd 200 sa1 (sig): signal in brackets may be routed to the socket connector, but is not used on the module data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 functional block diagramm 1 024m b ddr2 sdram sodimm, 1 rank and 8 com ponents i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 0 dqs cs dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 odt 0 dqs 0 dm 0 dqs 0 cke 0 odt cke i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 4 dqs cs dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dm 4 dqs 4 odt cke i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 1 dqs cs dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 dqs 1 dm 1 odt cke i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 5 dqs cs dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 dqs 5 dm 5 dqs 5 odt cke dqs 1 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 2 dqs cs dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 dqs 2 dm 2 odt cke dqs 2 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 3 dqs cs dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 dqs 3 dm 3 odt cke dqs 3 ba 0 - ba 2 : sdram d 0 - d 7 a 0 - a 13 : sdram d 0 - d 7 ras : sdram d 0 - d 7 cas : sdram d 0 - d 7 we : sdram d 0 - d 7 ba 0 - ba 2 a 0 - a 13 ras cas we i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 6 dqs cs dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 odt cke i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs d 7 dqs cs dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 odt cke dqs 6 dm 6 dqs 6 dqs 7 dm 7 dqs 7 v ddspd spd v ref d 0 - d 7 v dd d 0 - d 7 d 0 - d 7 / spd v ss data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any pin relative to v ss v in , v out - 0.5 2.3 v inp ut leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage current (dqs and odt are dis abled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v capacita nce at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic t han a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets. data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 i dd specifications and conditions (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test condition symbol max unit 5300 - 555 6400 - 666 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between v alid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 344 360 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck ( i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 384 408 ma precharge power - down current: all device ba nks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 80 80 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 160 160 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every t wo clock cycles; dq inputs changing once per clock cycle i dd2n 192 200 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit mr[12] = 0 i dd3p 184 176 ma slow pdn exit mr[12] = 1 120 120 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 240 256 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 560 640 ma data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 parameter & test condition symbol m ax unit 5300 - 555 6400 - 666 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between vali d commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 480 536 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 800 840 ma self refresh current: ck and ck# at 0v; cke 0.2v ; all other control and address bus inputs are floatin g at v ref ; dqs are floating at v ref i dd6 80 80 ma operating current *) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); ck e is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1160 1280 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 53 00 - 555 6400 - 666 unit cl (i dd ) 5 6 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 3.0 2.5 ns t ras min (i dd ) 45 45 ns t ra s max (i dd ) 70 000 70 000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 127 127 ns data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 6400 - 666 unit parameter symbol min max min max clock cycle time cl = 6 t ck (6) - - 2.5 8.0 ns cl = 5 t ck (5) 3.0 8.0 3.0 8.0 ns cl = 4 t ck (4) 3.7 5 8.0 3.75 8.0 ns cl = 3 t ck (3) 5.0 8.0 - - ns ck high - level width t ch 0.48 0.52 0.48 0.52 t ck ck low - level width t cl 0.48 0.52 0.48 0.52 t ck half clock period t hp min (t ch, t cl ) min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac - 0.45 +0.45 - 0.40 +0.40 ns data - out high - impedance window from ck/ck# t hz +0.45 (= t ac max) +0.40 (= t ac max) ns data - out low - impedance window from ck/ck# t lz - 0.45 (= t ac min) +0.45 (= t ac max) - 0.40 (= t ac min) +0.40 (= t ac max) ns dq and dm input s etup time relative to dqs t ds (base) 0.10 0.05 ns dq and dm input hold time relative to dqs t dh (base) 0.30 0.125 ns dq and dm input pulse width ( for each input ) t dipw 0.35 0.35 t ck data hold skew factor t qhs 0.34 0.3 ns dq - dqs hold, dqs to fi rst dq to go non - valid, per access t qh t hp - t qhs t hp - t qhs ns data valid output window t dvw t qh - t dqsq t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck - 0.40 +0.40 - 0.35 +0.35 ns dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs C t dqsq 0.24 0.2 ns dqs re ad preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dqs write preamble t wpre 0.35 0.35 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck positive dqs latching edge to assoc iated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck write command to first dqs latching transition wl - t dqss wl+ t dqss wl - t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 0.6 t ck data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electric al characteristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 6400 - 666 unit parameter symbol min max min max address and control input setup time t is (base) 0.20 0.175 ns address and control input hold time t ih (base) 0.275 0.250 ns cas# to cas# command delay t ccd 2 2 t ck active to active (same bank) command period t rc 55 60 ns active bank a to active bank b command t rrd 7.5 7.5 ns active to read or write delay t rcd 15 15 ns four bank activate period t fa w 37.5 37.5 ns active to precharge command t ras 45 70 t rtp 7.5 7.5 ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns inter nal write to read command delay t wtr 7.5 7.5 ns precharge command period t rp 15 15 ns precharge all command period t rpa t rp + t ck t rp + t ck ns load mode command cycle time t mrd 2 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 127 127 ns average periodic refresh interval (0c data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 6400 - 666 unit parameter symbol min max min max odt power - down exit latency t axpd 8 8 t ck odt enable from mrs command t mod 12 12 ns exit active power - down to read command, mr [bit 12 = 0] t xard 2 2 t ck exit active power - down to read command, mr [bit 12 = 1] t xards 7 C C ck exit precharge power - down to any non - read command t xp 2 2 t ck cke minimum high/low time t cke 3 3 t ck data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 serial p resence - detect matrix byte description 5300 - 555 6400 - 666 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x 08 2 fundamental memory type 0x 08 3 number of row addresses on assembly 0x 0e 4 number of column addresses on assembly 0x 0a 5 dimm hight and module ranks 0x60 6 module data width 0x 40 7 module data width (continued) 0x 00 8 module voltage interface levels (v dd q ) 0x 05 9 sdram cycle time, (t ck ) [max cl] 0x 30 0x25 10 sdram access from clock, (t ac ) [max cl] 0x 45 0x40 11 module configuration type 0x 00 12 refresh rate / type 0x 82 13 sdram device width (primary sdram) 0x 08 14 error - checking sdram data width 0x 00 15 minimum clock delay, back - to - back random column access 0x 00 16 burst lengths supported 0x 0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x 38 0x70 19 module thickness 0x 01 20 ddr2 dimm type 0x 04 21 sdram module attributes 0x 00 22 sdram device attributes: weak driver and 50 odt 0x 07 23 sdram cycle time, (t ck ) [max cl C 1] 0x 3d 0 x30 24 sdram access from ck, (t ac ) [max cl C 1] 0x 50 0x45 25 sdram cycle time, (t ck ) [max cl C 2] 0x 50 0x3d 26 sdram access from ck, (t ac ) [max cl C 2] 0x 60 0x50 27 minimum row precharge time, (t rp ) 0x 3c 28 minimum row active to row active, (t rrd ) 0x 1 e 29 minimum ras# to cas# delay, (t rcd ) 0x 3c 30 minimum ras# pulse width, (t ras ) 0x 2d 31 module bank density 0x 01 data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 serial presence - d e tect matrix (continued) byte description 5300 - 555 6400 - 666 32 address and command setup time, (t isb ) 0x 20 0x17 33 a ddress and command hold time, (t ihb ) 0x 27 0x25 34 data / data mask input setup time, (t dsb ) 0x 10 0x05 35 data / data mask input hold time, (t dhb ) 0x 17 0x12 36 write recovery time, (t wr ) 0x 3c 0x3c 37 write to read command delay, (t wtr ) 0x 1e 0x1e 38 rea d to precharge command delay, (t rtp ) 0x 1e 0x1e 39 mem analysis probe 0x 00 40 extension for bytes 41 and 42 0x 06 41 min active auto refresh time, (t rc ) 0x 3c 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x 7f 43 sdram device m ax cycle time, (t ckmax ) 0x 80 44 sdram device max dqs - dq skew time, (t dqsq ) 0x 18 0x14 45 sdram device max read data hold skew factor, (t qhs ) 0x 22 0x1e 46 pll relock time 0x 00 47 - 61 optional features, not supported 0x 00 62 spd revision 0x 13 63 checksum for bytes 0 - 62 0x 1 9 0xe3 64 - 66 manufacturer`s jedec id code 0x 7f 6 7 manufacturer`s jedec id code (continued) 0x da 68 - 71 manufacturer`s jedec id code (continued) 0x00 72 manufacturing location xx 73 - 90 module part number (ascii) sen01g64d1bf 1sa - xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) x 128 - 255 open for customer use 0xff part numbe r code s e n 01g 64 d1 b f 1 sa - 25 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2 - 800 mt/s sdram d dr 2 200 pin unbuffered 1.8v chip vendor (samsung) depth (1g b) 1 module rank width chip rev. f pcb - type ( 8231a ) chip organisation x8 * optional / additional information data sheet rev.1. 2 12.12 .2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 72 66 fax: +41 (0 )71 913 74 50 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 14 willett avenue, suite 301a port c hester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 302 9001 fax: +1 512 302 4808 |
Price & Availability of SEN01G64D1BF1SA-25R
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